1. Field of the Disclosure
The present invention relates to NAND flash memory devices and, more specifically, to a NAND flash memory device capable of changing a block size by dividing a single block into two blocks.
2. Description of Related Technology
A memory cell array embedded in a NAND flash memory device includes a number of memory blocks, each block including a plurality of memory strings. Each string is constructed of a drain selection transistor connected to a bitline, a source selection transistor connected to a common source line, and a plurality of memory cells connected between the selection transistors serially.
The string is sized in a regularized dimension with 16 or 32 memory cells. Thus, a size of the memory block is determined in a constant dimension.
In typical NAND flash memory devices, a programming or reading operation is carried out in the unit of page, while an erasing operation is carried out in the unit of block (or sector). In other words, an erasing operation erases all memory cells belonging to a block of the constant size.
However, because the design of the memory array and peripheral circuits may need to be modified when reducing the block size, such changes to the block size may be problematic.